Hardware Accelerator for Raptor Decoder

Hard Raptor Codes (designed for erasure channels) are widely used for mobile multimedia content delivery, and yet they have not been investigated in the context of embedded systems where the energy dissipation is as important as the timing performance. The most time consuming part of Raptor decoder is the matrix inversion operation. This paper proposes a hardware accelerator, for two matrix inversion algorithms, as a part of Raptor decoder implemented on a system on a chip (SoC) platform with a soft-core embedded processor. The performance, energy profile and resource implication are analyzed and compared with a pure software implementation.